﻿#region Using directives

using System;

using Weazel.Badger.Vhdl;
using Weazel.Badger.Vhdl.Types;
using Weazel.Badger.Vhdl.Operators;
using Weazel.Badger.Vhdl.Statements;
using Weazel.Badger.Vhdl.Expressions;

#endregion

namespace Weazel.Badger
{
  public class SimulationSystemEntity : SystemEntity
  {
    private Signal clockSignal;
		private Signal resetSignal;

    public SimulationSystemEntity(ConversionContext context, Gezel.Model.Model model, Gezel.Model.system system)
      : base(context, model, system)
    {
			clockSignal = new Signal(new StdLogic(), null, context.Configuration.ClockName);
			resetSignal = new Signal(new StdLogic(), null, context.Configuration.ResetName);
    }

    public void Convert()
    {
      CreateSignals();

      clockSignal.Type = new StdLogic();
      AddSignal(clockSignal);
      AddDeclarativeItem(clockSignal);

      resetSignal.Type = new StdLogic();
      AddSignal(resetSignal);
      AddDeclarativeItem(resetSignal);

      CreateComponentDeclarations(clockSignal, resetSignal);
      CreatePortMaps(clockSignal, resetSignal);

			if(context.Configuration.CreateClockAndResetGenerationProcesses)
				CreateClockAndResetGenerationProcess(clockSignal, resetSignal);
    }

    protected override void OnUnconnectedInputNetFound(Weazel.Gezel.Model.system.Net net)
    {
      System.Diagnostics.Debug.Assert(net.OutPort != null);

      Vhdl.Types.Type t = net.OutPort.Width == 1 ?
          (Vhdl.Types.Type)new StdLogic()
        : (Vhdl.Types.Type)new StdLogicVector(net.OutPort.Width);

      Signal signal = new Signal(t, new GezelType(net.OutPort.Signed, net.OutPort.Width), net.LocalName);

      AddSignal(signal);
      AddDeclarativeItem(signal);
    }

    protected override void OnUnconnectedOutputNetFound(Weazel.Gezel.Model.system.Net net)
    {     
    }
  }
}
